Methods for fabricating reinforced, self-aligning conductive structures for semiconductor device components

ABSTRACT

A method for fabricating an electrical interconnection element, or conductive structure, includes disposing a jacket of a first member of the electrical interconnection element laterally around a contact of a semiconductor device structure and introducing conductive material into the jacket. The jacket, which may be electrically insulative, may include a plurality of adjacent, mutually adhered regions. Such regions may be formed by programmed material consolidation processes, such as stereolithography, in which material is selectively consolidated in a manner controlled by a program. The first member is configured to interconnect with a second member of the electrical interconnection element, which may be secured to and electrically communicate with a contact of another semiconductor device component.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of application Ser. No. 09/590,646,filed Jun. 8, 2000, pending. The disclosure of the previously referencedU.S. patent application referenced is hereby incorporated by referencein its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to conductive structures for usewith semiconductor device components, such as flip-chip typesemiconductor devices, including chip-scale packages. Particularly, thepresent invention pertains to complementarily configured and locatedconductive structures on a semiconductor device and another substrate towhich the semiconductor device is to be connected. The invention alsorelates to methods of fabricating the conductive structures and, moreparticularly, to the use of stereolithography to fabricate at least aportion of the conductive structures.

2. State of the Art

Conductive Structures Used to Connect a Semiconductor Device Face Downto a Higher Level Substrate

Some types of semiconductor devices, such as flip-chip typesemiconductor devices, including flip-chip type dice and ball grid array(BGA) packages (including chip-scale packages, or CSPs), can beconnected to higher level substrates by orienting these semiconductordevices face down over the higher level substrate. The contact pads ofsuch semiconductor devices are typically connected directly tocorresponding contact pads of the higher level substrate by solderballs.

Examples of solders that are known in the art to be useful in connectingsemiconductor devices face down to higher level substrates include, butare not limited to, lead-tin (Pb/Sn) solder, silver-nickel (Ag/Ni)solder, copper, gold, and conductive or conductor-filled polymers. Forexample, 95/5 type Pb/Sn solder bumps (i.e., solder having about 95% byweight lead and about 5% by weight tin) have been used in flip-chip andball grid array type attachments, including chip-scale packages (CSPs).

When 95/5 type Pb/Sn solder bumps are employed as conductive structuresto form a direct connection between a contact pad of a semiconductordevice and a contact pad of a higher level substrate, a quantity ofsolder paste having a higher melting temperature, such as 63/37 typePb/Sn solder, can be applied to the contact pad of the higher levelsubstrate to facilitate bonding of the solder bump thereto. As the 95/5type Pb/Sn solder and the 63/37 type Pb/Sn solder are heated to bond thesolder bump to a contact pad of the substrate, the 95/5 type Pb/Snsolder, which has a lower melting temperature, softens first. Thus, thegravitational or compressive forces holding the semiconductor device inposition over the higher level substrate can cause the softened 95/5type Pb/Sn solder bump to flatten, pushing the solder laterally outwardonto portions of the surface of the semiconductor device that surroundthe contact pad to which the solder bump is secured.

Further, when solder balls are reflowed to connect a semiconductordevice to a substrate, a phenomenon referred to as “outgassing” occurs,which can damage a semiconductor device proximate to the solder balls.Moreover, relatively high temperatures are required to reflow even lowtemperature solders, such as 95/5 type Pb/Sn solders. The reflowtemperatures can damage package components, such as packaging orencapsulant materials, and even features of the semiconductor die beingconnected to the substrate.

Assemblies that include semiconductor devices connected face down tohigher level substrates are subjected to thermal cycling during furtherprocessing, testing thereof, and in normal use. As these assembliesundergo thermal cycling, the solder balls thereof are also exposed towide ranges of temperatures, causing the solder balls to expand whenheated and contract when cooled. Solder balls have a very differentcoefficient of thermal expansion than the primary materials of thesemiconductor device and the substrate between which the solder ballsare disposed. Thus, the amount that the solder balls expand and contractdiffers significantly from the amount of expansion and contraction ofthe semiconductor device and the substrate. As a result, repeatedvariations in temperatures can cause solder fatigue, which can reducethe strength of the solder balls, cause the solder balls to fail, anddiminish the reliability of the solder balls. Thermal cycling can alsoalter the conformations of the conductive structures.

The likelihood that a solder ball will be damaged by thermal cycling isparticularly high when the solder ball spreads over and contacts thesurface of the semiconductor device or the higher level substratesurrounding the contact pad. The solder ball loses some of its abilityto dissipate heat and, therefore, can be exposed to the full range oftemperatures that can occur during thermal cycling. Thus, flattenedsolder balls and solder balls that contact regions of the surface of asemiconductor device that surround the contact pads thereof areparticularly susceptible to the types of damage that can be caused bythermal cycling of the semiconductor device.

Furthermore, when solder balls contact regions of the semiconductordevice that surround the contact pads to which the solder balls aresecured, undesirable parasitic capacitance can occur.

In an attempt to increase the reliability with which solder ballsconnect semiconductor devices face down to higher level substrates,resins have been applied to semiconductor devices to form collars aroundthe bases of the solder balls protruding from the semiconductor devices.These resinous supports laterally contact the bases of the solder ballsto enhance the reliability thereof. The resinous supports are applied toa semiconductor device after solder balls have been secured to thecontact pads of the semiconductor device and before the semiconductordevice is connected face down to a higher level substrate. As those ofskill in the art are aware, however, the shapes of solder balls canchange when bonded to the contact pads of a substrate. If the shapes ofthe solder balls change, the solder balls can fail to maintain contactwith the resinous supports, which could thereby fail to protect orenhance the reliability of the solder balls.

The use of solder balls in connecting a semiconductor device face downto higher level substrates is also somewhat undesirable from thestandpoint that, due to their generally spherical shapes, solder ballsconsume a great deal of area, or “real estate,” on a semiconductordevice. Thus, solder balls can unduly limit the minimum spacing betweenthe adjacent contact pads of a semiconductor device and, thus, theminimum pitch of the contact pads on the semiconductor device.

Other types of conductive structures have been used to connectsemiconductor devices, including those with relatively tight contact padpitches, to substrates. Examples of these alternative conductivestructures include pillars of conductive elastomer or conductor filledepoxy. When such conductive pillars are secured to the contact pads of asemiconductor device, however, the conductive materials from which theseconductive structures are fabricated can bleed. This may cause thematerial to flow onto regions of the semiconductor device surroundingthe contact pad, which may cause parasitic capacitance or evenelectrical shorts when adjacent conductive structures bleed into contactwith each other or a conductive structure bleeds onto an adjacentcontact pad.

The use of other conductive structures which have more desirable shapes,such as pillars, or columns, and mushroom-type shapes, and consume lessconductive material than solder balls, to connect semiconductor devicesface down to higher level substrates, has been limited since thesetaller and thinner conductive structures are typically made frommaterials that do not retain their shapes upon being bonded to thecontact pads of a higher level substrate or in thermal cycling of thesemiconductor device.

The inventors are not aware of any art that discloses reinforced,self-aligning conductive structures that facilitate the connection of asemiconductor device to a substrate while preventing conductive materialfrom bleeding or flowing over the edges of contact pads to which theconductive structures are secured. Moreover, the inventors are not awareof methods that can be used to fabricate such reinforced conductivestructures.

Stereolithography

In the past decade, a manufacturing technique termed“stereolithography,” also known as “layered manufacturing,” has evolvedto a degree where it is employed in many industries.

Essentially, stereolithography, as conventionally practiced, involvesutilizing a computer to generate a three-dimensional (3-D) mathematicalsimulation or model of an object to be fabricated, such generationusually effected with 3-D computer-aided design (CAD) software. Themodel or simulation is mathematically separated or “sliced” into a largenumber of relatively thin, parallel, usually vertically superimposedlayers, each layer having defined boundaries and other featuresassociated with the model (and thus the actual object to be fabricated)at the level of that layer within the exterior boundaries of the object.A complete assembly or stack of all of the layers defines the entireobject, and surface resolution of the object is, in part, dependent uponthe thickness of the layers.

The mathematical simulation or model is then employed to generate anactual object by building the object, layer by superimposed layer. Awide variety of approaches to stereolithography by different companieshas resulted in techniques for fabrication of objects from both metallicand nonmetallic materials. Regardless of the material employed tofabricate an object, stereolithographic techniques usually involvedisposition of a layer of unconsolidated or unfixed materialcorresponding to each layer within the object boundaries. This isfollowed by selective consolidation or fixation of the material to atleast a partially consolidated, or semisolid, state in those areas of agiven layer corresponding to portions of the object, the consolidated orfixed material also at that time being substantially concurrently bondedto a lower layer of the object to be fabricated. The unconsolidatedmaterial employed to build an object may be supplied in particulate orliquid form, and the material itself may be consolidated or fixed or aseparate binder material may be employed to bond material particles toone another and to those of a previously formed layer. In someinstances, thin sheets of material may be superimposed to build anobject, each sheet being fixed to a next lower sheet and unwantedportions of each sheet removed, a stack of such sheets defining thecompleted object. When particulate materials are employed, resolution ofobject surfaces is highly dependent upon particle size, whereas when aliquid is employed, surface resolution is highly dependent upon theminimum surface area of the liquid which can be fixed and the minimumthickness of a layer that can be generated. Of course, in either case,resolution and accuracy of object reproduction from the CAD file is alsodependent upon the ability of the apparatus used to fix the material toprecisely track the mathematical instructions indicating solid areas andboundaries for each layer of material. Toward that end, and dependingupon the layer being fixed, various fixation approaches have beenemployed, including particle bombardment (electron beams), disposing abinder or other fixative (such as by ink-jet printing techniques), orirradiation using heat or specific wavelength ranges.

An early application of stereolithography was to enable rapidfabrication of molds and prototypes of objects from CAD files. Thus,either male or female forms on which mold material might be disposedmight be rapidly generated. Prototypes of objects might be built toverify the accuracy of the CAD file defining the object and to detectany design deficiencies and possible fabrication problems before adesign was committed to large-scale production.

In more recent years, stereolithography has been employed to develop andrefine object designs in relatively inexpensive materials, and has alsobeen used to fabricate small quantities of objects where the cost ofconventional fabrication techniques is prohibitive for same, such as inthe case of plastic objects conventionally formed by injection molding.It is also known to employ stereolithography in the custom fabricationof products generally built in small quantities or where a productdesign is rendered only once. Finally, it has been appreciated in someindustries that stereolithography provides a capability to fabricateproducts, such as those including closed interior chambers or convolutedpassageways, which cannot be fabricated satisfactorily usingconventional manufacturing techniques. It has also been recognized insome industries that a stereolithographic object or component may beformed or built around another, pre-existing object or component tocreate a larger product.

However, to the inventors' knowledge, stereolithography has yet to beapplied to mass production of articles in volumes of thousands ormillions, or employed to produce, augment or enhance products includingother, pre-existing components in large quantities, where minutecomponent sizes are involved, and where extremely high resolution and ahigh degree of reproducibility of results is required. In particular,the inventor is not aware of the use of stereolithography in thefabrication of conductive structures protruding from the contact pads ofsemiconductor devices, such as flip-chip type semiconductor devices orchip-scale packages. Furthermore, conventional stereolithographyapparatus and methods fail to address the difficulties of preciselylocating and orienting a number of pre-existing components forstereolithographic application of material thereto without the use ofmechanical alignment techniques or to otherwise assuring precise,repeatable placement of components.

SUMMARY OF THE INVENTION

The present invention includes a reinforced, self-aligning conductivestructure. The conductive structure includes interconnectable male andfemale members, each having a conductive center and a dielectric jacketformed from a thermally stable resin surrounding the conductive center.

In one embodiment, the female member of the reinforced, self-aligningconductive structure is secured to or fabricated on a contact pad of oneof a semiconductor device and a substrate, while the male member issecured to or fabricated on a corresponding contact pad of the other oneof the substrate and the semiconductor device. Each of the male andfemale members include an outer dielectric support component thatcontains a quantity of conductive material in contact with the contactpad over which each of the members is disposed. The female member has arecess configured complementarily to at least an end of the male memberso as to receive the end of the male member. Upon connection of thefemale and male members, the conductive center portions of the memberscontact each other to place the corresponding contact pads of thesemiconductor device and the substrate in electrical communication witheach other.

According to another aspect, the invention includes a method for joiningthe conductive centers of an assembled male member and female member.The conductive material of each of the male and female members ispreferably a thermally curable polymer. Preferably, the material of atleast one of the conductive centers is at least partially uncured. Oncethe male and female members have been assembled, the material of theconductive centers can be fully cured to form an integral conductivecenter between a contact pad of the semiconductor device and acorresponding contact pad of the substrate. In addition, curing theconductive material of the male and female members following assemblythereof secures the semiconductor device to the substrate.

Alternatively, other conductive materials, such as solders, metals, ormetal alloys, can be employed as the conductive centers of each of themale and female members. The conductive centers of an interconnectedmale member and female member can be formed into an integral conductivecenter by reflowing the material of the conductive centers.

A conductive structure incorporating teachings of the present inventionsurrounds the periphery of a contact pad exposed at the surface of asemiconductor device or substrate to confine the conductive materialover the contact pad and to prevent the conductive material frombleeding or flowing onto portions of the surface of the semiconductordevice or substrate that surround the contact pad.

According to another aspect, the present invention includes a method forfabricating the reinforced conductive structure according to the presentinvention. In a preferred embodiment of the method, acomputer-controlled, 3-D CAD initiated process known as“stereolithography” or “layered manufacturing” is used to fabricate thejacket of both the male and female members. When stereolithographicprocesses are employed, each jacket is formed as either a single layeror a series of superimposed, contiguous, mutually adhered layers ofmaterial.

The stereolithographic method of fabricating the jackets of the presentinvention preferably includes the use of a machine vision system tolocate the semiconductor devices or substrates on which the jackets areto be fabricated, as well as the features or other components on orassociated with the semiconductor devices or substrates (e.g., contactpads, conductive traces, etc.). The use of a machine vision systemdirects the alignment of a stereolithography system with eachsemiconductor device or substrate for material disposition purposes.Accordingly, the semiconductor devices or substrates need not beprecisely mechanically aligned with any component of thestereolithography system to practice the stereolithographic embodimentof the method of the present invention.

In a preferred embodiment, the jackets to be fabricated or positionedupon and secured to a semiconductor device component in accordance withthe invention are fabricated using precisely focused electromagneticradiation in the form of an ultraviolet (UV) wavelength laser undercontrol of a computer and responsive to input from a machine visionsystem, such as a pattern recognition system, to fix or cure selectedregions of a layer of a liquid photopolymer material disposed on thesemiconductor device or substrate.

The jackets may be fabricated either separately from the semiconductordevice or substrate to which they are to be secured or directly on thesemiconductor device or substrate. If the jackets are fabricateddirectly on the semiconductor device or substrate, they may befabricated around pre-formed quantities of conductive materialprotruding from the contact pads of the semiconductor device orsubstrate. Alternatively, the jackets may be fabricated around or overthe peripheries of contact pads of the semiconductor device or substratewith the contact pads being exposed therethrough. Conductive materialmay then be disposed in the jackets and against the contact pads exposedtherethrough.

Following the fabrication of a hollow jacket, a quantity ofunconsolidated (e.g., particulate, molten, or uncured liquid) conductiveor conductor-filled material is disposed in the centers of the jackets.Alternatively, stereolithography may also be used to form the conductivecenters of the male and female members from an electrically conductivephotopolymer. If stereolithography is used to fabricate the conductivecenters, the conductive center of at least one of a corresponding pairof members is preferably left at least partially unconsolidated so as tofacilitate the subsequent formation of an integral conductive centerthrough the conductive structure.

Other features and advantages of the present invention will becomeapparent to those of skill in the art through consideration of theensuing description, the accompanying drawings, and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a semiconductor device having malemembers of conductive structures protruding from the contact padsthereof and a carrier substrate having corresponding female members ofthe conductive structures protruding from the contact pads thereof;

FIG. 2 is an enlarged partial perspective view of a male member on thesemiconductor device of FIG. 1;

FIG. 3 is an enlarged partial perspective view of a female member on thesubstrate of FIG. 1;

FIG. 4 is a bottom plan view of the semiconductor device of FIG. 1;

FIG. 5 is a bottom plan view of the substrate of FIG. 1;

FIG. 6 is a cross-sectional view depicting the semiconductor device andthe substrate of FIG. 1 in an assembled relationship with the malemembers and the female members interconnected;

FIG. 7 is a cross-sectional view depicting a semiconductor device and asubstrate having another embodiment of the male and female members ofthe conductive structure in communication with a contact pad thereof;

FIG. 8 is a cross-sectional view depicting another embodiment of theconductive structure, with the male and female members thereof securedto corresponding contact pads of a semiconductor device and a substrate;

FIG. 9 is a cross-sectional view depicting yet another embodiment of theconductive structure, with the male and female members thereof securedto corresponding contact pads of a semiconductor device and a substrate;

FIG. 10 is a perspective view of a portion of a wafer having a pluralityof semiconductor devices thereon, depicting female members of theconductive structures being fabricated around each of the contact padsof the semiconductor devices at the wafer level;

FIG. 11 is a schematic representation of an exemplary stereolithographyapparatus that can be employed in the method of the present invention tofabricate the jacket of a male member of a conductive structure of thepresent invention; and

FIG. 12 is a partial cross-sectional side view of a semiconductor devicedisposed on a platform of a stereolithographic apparatus for theformation of jackets of a male member of a conductive structure aroundthe contact pads of the semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION Conductive Structures

With reference to FIGS. 1 and 4-6, a semiconductor device assembly 10,including a semiconductor device 10 and a substrate 20, is shown.Semiconductor device 10 is a flip-chip type device, such as a flip-chipdie or a ball grid array package, or a flip-chip type chip-scale packagehaving contact pads 12 (FIG. 6) on a surface 14 thereof that can each bebonded to corresponding contact pads 22 (FIG. 6) of a surface 24 ofsubstrate 20 by way of conductive structures 30.

Each conductive structure 30 has a separate, interconnectable malemember 40 and female member 50. As illustrated, male members 40 aresecured to and protrude from contact pads 12 of semiconductor device 10,while female members 50 are secured to and protrude from contact pads 22of substrate 20.

Referring now to FIGS. 2 and 6, male members 40 each include adielectric jacket 42 with an aperture 44 extending through the lengththereof. Aperture 44 is filled with a quantity of conductive material,referred to herein as a conductive center 46 of male member 40.Preferably, aperture 44 is completely filled with conductive material.Jacket 42 and aperture 44 are configured to contain the material ofconductive center 46 over a contact pad 12 and to, therefore, preventthe material of conductive center 46 from bleeding or flowing off ofcontact pads 12 and onto the surrounding areas of surface 14. Jacket 42also electrically insulates the lateral periphery of conductive center46.

FIGS. 3 and 6 illustrate female members 50, each of which has adielectric jacket 52 with an aperture 54 extending through the lengththereof. As with male member 40, jacket 52 and aperture 54 areconfigured to contain the conductive material of conductive center 56over a contact pad 22 of substrate 20 and to prevent the material ofconductive center 56 from bleeding or flowing off of contact pads 22 andonto surrounding areas of surface 24. Jacket 52 also electricallyinsulates the lateral surfaces of conductive center 56. Unlike aperture44 of male member 40, aperture 54 is preferably only partially filledwith conductive material to form a conductive center 56 of female member50. An upper portion 58 of aperture 54, which is preferably not filledwith conductive material, is configured to matingly receive at least anend portion of male member 40. Upper portion 58 is also referred toherein as a receptacle.

Turning to FIG. 7, an alternative embodiment of a conductive structure30′ incorporating teachings of the present invention is illustrated.Conductive structure 30′ has a male member 40′, illustrated as beingsecured over a contact pad 12 of semiconductor device 10, and a femalemember 50′, which, as illustrated, is secured to a contact pad 22 ofsubstrate 20.

As illustrated, the periphery of the end portion 43′ of jacket 42′ issmaller than the periphery of the remainder of jacket 42′, with an outerledge 48 being formed at the junction between end portion 43′ and theremainder, or base portion 45′, of jacket 42′. When male member 40′ isinterconnected with female member 50′, a complementarily configuredupper portion 58′ of aperture 54′ receives end portion 43′ of malemember 40′ and ledge 48 prevents further insertion of male member 40′into aperture 54′ of female member 50′. Thus, outer ledge 48 defines aminimum length of conductive structure 30′ and a minimum distancebetween an assembled semiconductor device 10 and substrate 20.

With continued reference to FIG. 7, in addition to male member 40′including an outer ledge 48, or alternatively thereto, upper portion 58′of aperture 54′ can have a larger periphery than the remainder ofaperture 54′, with an internal ledge 55 being formed at the junctionbetween upper portion 58′ and the remainder of aperture 54′. Internalledge 55 acts as a stop for male member 40′ during insertion thereofinto aperture 54′ and prevents male member 40′ from being inserted toofar into aperture 54′ of female member 50′. Internal ledge 55 may alsobe used as a line of demarcation to identify an optimum level forfilling aperture 54′ with conductive material so as to facilitate anelectrical communication between a contact pad 12 of semiconductordevice 10 and a corresponding contact pad 22 of substrate 20 whileavoiding the use of an excessive quantity of conductive material as malemember 40′ and female member 50′ are interconnected.

FIG. 8 illustrates another embodiment of a conductive structure 30″according to the present invention, wherein the larger end of afrustoconically shaped or otherwise tapered male member 40″ thereof issecured to a contact pad 22 of substrate 20 and the female member 50″thereof is secured to a contact pad 12 of semiconductor device 10.Female member 50″ has an aperture 54″ configured to receive at least anend portion 43″ of the jacket 42″ of male member 40″. The tapering ofthe outer surface of jacket 42″ facilitates self-alignment of malemember 40″ and female member 50″ when semiconductor device 10 andsubstrate 20 are not precisely and accurately aligned. In addition,jacket 42″ may be tapered and aperture 54″ sized so as to permit malemember 40″ to insert only a predetermined, specific distance intoaperture 54″ of female member 50″ and, thus, define a minimum length ofconductive structure 30″, as well as a minimum assembled distancebetween semiconductor device 10 and substrate 20.

Yet another embodiment of a conductive structure 30′″ according to thepresent invention is illustrated in FIG. 9. The male and female members40′″, 50′″, respectively, of conductive structure 30′″ each havesubstantially cylindrical shapes. The outer surface of the jacket 42′″of end 43′″ of male member 40′″, remote from semiconductor device 10 towhich male member 40′″ is secured, tapers inwardly toward the center ofmale member 40′″. Female member 50′″ has an aperture 54′″ with an innersurface and an end remote from substrate 20 to which female member 50′″is secured that tapers outwardly toward a periphery of female member50′″. The tapered ends 43′″, 53′″ of male member 40′″ and female member50′″, respectively, are complementarily configured, thereby facilitatingthe receipt of end 43′″ by end 53′″. Accordingly, upon interconnectionof male member 40′″ and female member 50′″, conductive structure 30′″has a substantially cylindrical shape.

Turning now to FIG. 10, a wafer 72 with a plurality of semiconductordevices 10 thereon is illustrated. Each semiconductor device 10, whichhas yet to be singulated, or diced, from wafer 72, has female members 50of conductive structures 30 secured to the contact pads 12 (see FIG. 8)thereof. Each semiconductor device 10 on wafer 72 is separated fromadjacent semiconductor devices 10 by a street 74.

While the jackets of the male and female members of the conductivestructures according to the present invention, including jackets 42,42′, 42″, 52, 52′, 52″, are preferably substantially simultaneouslyfabricated on or secured to a collection of semiconductor devices 10 orsubstrates 20, such as prior to singulating semiconductor dice from awafer 72, the jackets of each of the members of the conductivestructures can also be fabricated on or secured to collections ofindividual semiconductor devices 10 or substrates 20, or to individualsemiconductor devices 10 or substrates 20. As another alternative, thejackets can be substantially simultaneously fabricated on or secured toa collection of different types of semiconductor devices 10 orsubstrates 20.

The jackets of both members of the conductive structures of the presentinvention can be fabricated directly on semiconductor devices 10 orsubstrates 20. Alternatively, the jackets can be fabricated separatelyfrom semiconductor devices 10 or substrates 20, then secured thereto asknown in the art, such as by the use of a suitable adhesive.

The jackets are preferably fabricated from a photo-curable polymer, or“photopolymer,” by stereolithographic processes. When fabricateddirectly on a semiconductor device 10 or substrate 20, the jackets canbe made either before or after preformed conductive centers 46, 56 areconnected to contact pads 12 of semiconductor device 10 or to contactpads 22 of substrate 20.

For simplicity, the ensuing description is limited to an explanation ofa method of fabricating jackets 52 on a semiconductor device 10 prior toplacing conductive material in contact with contact pads 12 ofsemiconductor device 10. As should be appreciated by those of skill inthe art, however, the method described herein is also useful forfabricating the jackets of other embodiments of the female member of aconductive structure according to the present invention on one or moresemiconductor devices or substrates, as well as for fabricating thejackets of any embodiment of a male member of a conductive structurethat incorporates teachings of the present invention on one or moresemiconductor devices or substrates.

Stereolithography Apparatus and Methods

FIG. 11 schematically depicts various components and operation of anexemplary stereolithography apparatus 80 to facilitate the reader'sunderstanding of the technology employed in implementation of the methodof the present invention, although those of ordinary skill in the artwill understand and appreciate that apparatus of other designs andmanufacture may be employed in practicing the method of the presentinvention. The preferred, basic stereolithography apparatus forimplementation of the method of the present invention, as well asoperation of such apparatus, are described in great detail in UnitedStates patents assigned to 3D Systems, Inc., of Valencia, Calif., suchpatents including, without limitation, U.S. Pat. Nos. 4,575,330;4,929,402; 4,996,010; 4,999,143; 5,015,424; 5,058,988; 5,059,021;5,059,359; 5,071,337; 5,076,974; 5,096,530; 5,104,592; 5,123,734;5,130,064; 5,133,987; 5,141,680; 5,143,663; 5,164,128; 5,174,931;5,174,943; 5,182,055; 5,182,056; 5,182,715; 5,184,307; 5,192,469;5,192,559; 5,209,878; 5,234,636; 5,236,637; 5,238,639; 5,248,456;5,256,340; 5,258,146; 5,267,013; 5,273,691; 5,321,622; 5,344,298;5,345,391; 5,358,673; 5,447,822; 5,481,470; 5,495,328; 5,501,824;5,554,336; 5,556,590; 5,569,349; 5,569,431; 5,571,471; 5,573,722;5,609,812; 5,609,813; 5,610,824; 5,630,981; 5,637,169; 5,651,934;5,667,820; 5,672,312; 5,676,904; 5,688,464; 5,693,144; 5,695,707;5,711,911; 5,776,409; 5,779,967; 5,814,265; 5,850,239; 5,854,748;5,855,718; 5,855,836; 5,885,511; 5,897,825; 5,902,537; 5,902,538;5,904,889; 5,943,235; and 5,945,058. The disclosure of each of theforegoing patents is hereby incorporated herein by this reference.

With continued reference to FIG. 11 and as noted above, a 3-D CADdrawing of an object to be fabricated in the form of a data file isplaced in the memory of a computer 82 controlling the operation ofapparatus 80 if computer 82 is not a CAD computer in which the originalobject design is effected. In other words, an object design may beeffected in a first computer in an engineering or research facility andthe data files transferred via wide or local area network, tape, disc,CD-ROM, or otherwise, as known in the art, to computer 82 of apparatus80 for object fabrication.

The data is preferably formatted in an STL (for STereoLithography) file,STL being a standardized format employed by a majority of manufacturersof stereolithography equipment. Fortunately, the format has been adoptedfor use in many solid-modeling CAD programs, so translation from anotherinternal geometric database format is often unnecessary. In an STL file,the boundary surfaces of an object are defined as a mesh ofinterconnected triangles.

Apparatus 80 also includes a reservoir 84 (which may comprise aremovable reservoir interchangeable with others containing differentmaterials) of an unconsolidated material 86 to be employed infabricating the intended object. In the currently preferred embodiment,the unconsolidated material 86 is a liquid, photo-curable polymer, or“photopolymer,” that cures in response to light in the UV wavelengthrange. The surface level 88 of material 86 is automatically maintainedat an extremely precise, constant magnitude by devices known in the artresponsive to output of sensors within apparatus 80 and preferably undercontrol of computer 82. A support platform or elevator 90, preciselyvertically movable in fine, repeatable increments in direction 116responsive to control of computer 82, is located for movement downwardinto and upward out of material 86 in reservoir 84.

An object may be fabricated directly on platform 90 or on a substratedisposed on platform 90. When the object is to be fabricated on asubstrate disposed on platform 90, the substrate may be positioned onplatform 90 and secured thereto by way of one or more base supports 122(see FIG. 12). Such base supports 122 may be fabricated before orsimultaneously with the stereolithographic fabrication of one or moreobjects on platform 90 or a substrate disposed thereon. These supports122 may support, or prevent lateral movement of, the substrate or objectbeing formed relative to a surface 100 of platform 90. Supports 122 mayalso provide a perfectly horizontal reference plane for fabrication ofone or more objects thereon, as well as facilitate the removal of asubstrate or formed object from platform 90 following thestereolithographic fabrication of one or more objects on the substrate.Moreover, where a so-called “recoater” blade 102 is employed to form alayer of material on platform 90 or a substrate disposed thereon,supports 122 can preclude inadvertent contact of recoater blade 102, tobe described in greater detail below, with surface 100 of platform 90.

Apparatus 80 has a UV wavelength range laser plus associated optics andgalvanometers (collectively identified as laser 92) for controlling thescan of laser beam 96 in the X-Y plane across platform 90. Laser 92 hasassociated therewith a mirror 94 to reflect beam 96 downwardly as beam98 toward surface 100 of platform 90. Beam 98 is traversed in a selectedpattern in the X-Y plane, that is to say, in a plane parallel to surface100, by initiation of the galvanometers under control of computer 82 toat least partially cure, by impingement thereon, selected portions ofmaterial 86 disposed over surface 100 to at least a partiallyconsolidated (e.g., semisolid) state. The use of mirror 94 lengthens thepath of the laser beam, effectively doubling same, and provides a morevertical beam 98 than would be possible if the laser 92 itself weremounted directly above platform surface 100, thus enhancing resolution.

Referring now to FIGS. 11 and 12, data from the STL files resident incomputer 82 is manipulated to build an object, such as jacket 52,illustrated in FIGS. 1, 3, and 5, or base supports 122, one layer at atime. Accordingly, the data mathematically representing one or more ofthe objects to be fabricated are divided into subsets, each subsetrepresenting a slice or layer of the object. The division of data iseffected by mathematically sectioning the 3-D CAD model into at leastone layer, a single layer or a “stack” of such layers representing theobject. Each slice may be from about 0.0001 to about 0.0300 inch thick.As mentioned previously, a thinner slice promotes higher resolution byenabling better reproduction of fine vertical surface features of theobject or objects to be fabricated.

When one or more base supports 122 are to be stereolithographicallyfabricated, supports 122 may be programmed as a separate STL file fromthe other objects to be fabricated. The primary STL file for the objector objects to be fabricated and the STL file for base support(s) 122 aremerged.

Before fabrication of a first layer for a support 122 or an object iscommenced, the operational parameters for apparatus 80 are set to adjustthe size (diameter if circular) of the laser light beam used to curematerial 86. In addition, computer 82 automatically checks and, ifnecessary, adjusts by means known in the art, the surface level 88 ofmaterial 86 in reservoir 84 to maintain same at an appropriate focallength for laser beam 98. U.S. Pat. No. 5,174,931, referenced above andpreviously incorporated herein by reference, discloses one suitablelevel control system. Alternatively, the height of mirror 94 may beadjusted responsive to a detected surface level 88 to cause the focalpoint of laser beam 98 to be located precisely at the surface ofmaterial 86 at surface level 88 if level 88 is permitted to vary,although this approach is more complex. Platform 90 may then besubmerged in material 86 in reservoir 84 to a depth equal to thethickness of one layer or slice of the object to be formed, and theliquid surface level 88 is readjusted as required to accommodatematerial 86 displaced by submergence of platform 90. Laser 92 is thenactivated so laser beam 98 will scan unconsolidated (e.g., liquid orpowdered) material 86 disposed over surface 100 of platform 90 to atleast partially consolidate (e.g., polymerize to at least a semisolidstate) material 86 at selected locations, defining the boundaries of afirst layer 122A of base support 122 and filling in solid portionsthereof. Platform 90 is then lowered by a distance equal to thickness ofsecond layer 122B, and laser beam 98 is scanned over selected regions ofthe surface of material 86 to define and fill in the second layer whilesimultaneously bonding the second layer to the first. The process maythen be repeated as often as necessary, layer by layer, until basesupport 122 is completed. Platform 90 is then moved relative to mirror94 to form any additional base supports 122 on platform 90 or asubstrate disposed thereon or to fabricate objects upon platform 90,base support 122, or a substrate, as provided in the control software.The number of layers required to erect support 122 or one or more otherobjects to be formed depends upon the height of the object or objects tobe formed and the desired layer thickness 108, 110. The layers of astereolithographically fabricated structure with a plurality of layersmay have different thicknesses.

If a recoater blade 102 is employed, the process sequence is somewhatdifferent. In this instance, surface 100 of platform 90 is lowered intounconsolidated (e.g., liquid) material 86 below surface level 88 adistance greater than a thickness of a single layer of material 86 to becured, then raised above surface level 88 until platform 90, a substratedisposed thereon, or a structure being formed on either platform 90 or asubstrate thereon, is precisely one layer's thickness below blade 102.Blade 102 then sweeps horizontally over platform 90 or (to save time) atleast over a portion thereof on which one or more objects are to befabricated to remove excess material 86 and leave a film of preciselythe desired thickness. Platform 90 is then lowered so that the surfaceof the film and material level 88 are coplanar and the surface of theunconsolidated material 86 is still. Laser 92 is then initiated to scanwith laser beam 98 and define the first layer 130. The process isrepeated, layer by layer, to define each succeeding layer 130 andsimultaneously bond same to the next lower layer 130 until all of thelayers of the object or objects to be fabricated are completed. A moredetailed discussion of this sequence and apparatus for performing sameis disclosed in U.S. Pat. No. 5,174,931, previously incorporated hereinby reference.

As an alternative to the above approach to preparing a layer of material86 for scanning with laser beam 98, a layer of unconsolidated (e.g.,liquid) material 86 may be formed on surface 100 of support platform 90,on a substrate disposed on platform 90, or on one or more objects beingfabricated by lowering platform 90 to flood material 86 over surface100, over a substrate disposed thereon, or over the highest completedlayer of the object or objects being formed, then raising platform 90and horizontally traversing a so-called “meniscus” blade horizontallyover platform 90 to form a layer of unconsolidated material having thedesired thickness over platform 90, the substrate, or each of theobjects being formed. Laser 92 is then initiated and a laser beam 98scanned over the layer of unconsolidated material to define at least theboundaries of the solid regions of the next higher layer of the objector objects being fabricated.

Yet another alternative to layer preparation of unconsolidated (e.g.,liquid) material 86 is to merely lower platform 90 to a depth equal tothat of a layer of material 86 to be scanned, and to then traverse acombination flood bar and meniscus bar assembly horizontally overplatform 90, a substrate disposed on platform 90, or one or more objectsbeing formed to substantially concurrently flood material 86 thereoverand to define a precise layer thickness of material 86 for scanning.

All of the foregoing approaches to liquid material flooding and layerdefinition and apparatus for initiation thereof are known in the art andare not material to the practice of the present invention, therefore, nofurther details relating thereto will be provided herein.

In practicing the present invention, a commercially availablestereolithography apparatus operating generally in the manner as thatdescribed above with respect to apparatus 80 of FIG. 11 is preferablyemployed, but with further additions and modifications as hereinafterdescribed for practicing the method of the present invention. Forexample and not by way of limitation, the SLA-250/50HR, SLA-5000 andSLA-7000 stereolithography systems, each offered by 3D Systems, Inc., ofValencia, Calif., are suitable for modification. Photopolymers believedto be suitable for use in practicing the present invention includeCibatool SL 5170 and SL 5210 resins for the SLA-250/50HR system,Cibatool SL 5530 resin for the SLA-5000 and 7000 systems, and CibatoolSL 7510 resin for the SLA-7000 system. All of these photopolymers areavailable from Ciba Specialty Chemicals Inc.

By way of example and not limitation, the layer thickness of material 86to be formed, for purposes of the invention, may be on the order ofabout 0.0001 to 0.0300 inch, with a high degree of uniformity. It shouldbe noted that different material layers may have different heights so asto form a structure of a precise, intended total height or to providedifferent material thicknesses for different portions of the structure.The size of the laser beam “spot” impinging on the surface of material86 to consolidate (e.g., cure) same may be on the order of 0.001 inch to0.008 inch. Resolution is preferably ±0.0003 inch in the X-Y plane(parallel to surface 100) over at least a 0.5 inch×0.25 inch field froma center point, permitting a high resolution scan effectively across a1.0 inch×0.5 inch area. Of course, it is desirable to have substantiallythis high a resolution across the entirety of surface 100 of platform 90to be scanned by laser beam 98, such area being termed the “field ofexposure,” and being substantially coextensive with the vision field ofa machine vision system employed in the apparatus of the invention asexplained in more detail below. The longer and more effectively verticalthe path of laser beam 96/98, the greater the achievable resolution.

Referring again to FIG. 11, it should be noted that apparatus 80 usefulin the method of the present invention includes a camera 140 which is incommunication with computer 82 and preferably located, as shown, inclose proximity to optics and mirror 94 located above surface 100 ofsupport platform 90. Camera 140 may be any one of a number ofcommercially available cameras, such as capacitive-coupled discharge(CCD) cameras available from a number of vendors. Suitable circuitry asrequired for adapting the output of camera 140 for use by computer 82may be incorporated in a board 142 installed in computer 82, which isprogrammed, as known in the art, to respond to images generated bycamera 140 and processed by board 142. Camera 140 and board 142 maytogether comprise a so-called “machine vision system” and, specifically,a “pattern recognition system” (PRS), operation of which will bedescribed briefly below for a better understanding of the presentinvention. Alternatively, a self-contained machine vision systemavailable from a commercial vendor of such equipment may be employed.For example, and without limitation, such systems are available fromCognex Corporation of Natick, Mass. For example, the apparatus of theCognex BGA Inspection Package™ or the SMD Placement Guidance Package™may be adapted to the present invention, although it is believed thatthe MVS-8000™ product family and the Checkpoint® product line, thelatter employed in combination with Cognex PatMax™ software, may beespecially suitable for use in the present invention.

It is noted that a variety of machine vision systems are in existence,examples of which and their various structures and uses are described,without limitation, in U.S. Pat. Nos. 4,526,646; 4,543,659; 4,736,437;4,899,921; 5,059,559; 5,113,565; 5,145,099; 5,238,174; 5,463,227;5,288,698; 5,471,310; 5,506,684; 5,516,023; 5,516,026; and 5,644,245.The disclosure of each of the immediately foregoing patents is herebyincorporated by this reference.

Stereolithographic Fabrication of the Jackets

In order to facilitate fabrication of one or more dielectric jackets 52in accordance with the method of the present invention with apparatus80, a data file representative of the size, configuration, thickness andsurface topography of, for example, a particular type and design ofsemiconductor device 10 or other substrate upon which one or morejackets 52 are to be mounted, is placed in the memory of computer 82.Also, as jackets 52 are configured to be interconnected withcomplementary jackets 42 (see FIGS. 1 and 6) of male members 40 onanother substrate, a data file representative of the substrate to whichmale members 42 are to be secured and the features thereof, as well as adata file representative of male members 40, may be placed in memory.

One or more semiconductor devices 10, wafers 72 (see FIG. 10), or othersubstrates may be placed on surface 100 of platform 90 for fabricationof one or more dielectric jackets 52 around contact pads 12 thereof. Ifone or more semiconductor devices 10, wafers 72, or other substrates areto be held on or supported above platform 90 by stereolithographicallyformed base supports 122, one or more layers of material 86 aresequentially disposed on surface 100 and selectively altered by use oflaser 92 to form base supports 122.

Camera 140 is then activated to locate the position and orientation ofeach semiconductor device 10, including those on a wafer 72 (see FIG.10), or other substrate upon which one or more dielectric jackets 52 areto be fabricated. The features of each semiconductor device 10, wafer72, or other substrate are compared with those in the data file residingin memory, the locational and orientational data for each semiconductordevice 10, wafer 72, or other substrate then also being stored inmemory. It should be noted that the data file representing the design,size, shape and topography for each semiconductor device 10 or othersubstrate may be used at this juncture to detect physically defective ordamaged semiconductor devices 10 or other substrates prior tofabricating jackets 52 thereon or before conducting further processingor assembly of semiconductor device 10 or other substrates. Accordingly,such damaged or defective semiconductor devices 10 or other substratescan be deleted from the process of fabricating jackets 52, from furtherprocessing, or from assembly with other components. It should also benoted that data files for more than one type (size, thickness,configuration, surface topography) of each semiconductor device 10 orother substrate may be placed in computer memory and computer 82programmed to recognize not only the locations and orientations of eachsemiconductor device 10 or other substrate, but also the type ofsemiconductor device 10 or other substrate at each location uponplatform 90 so that material 86 may be at least partially consolidatedby laser beam 98 in the correct pattern and to the height required todefine jackets 52 in the appropriate, desired locations on eachsemiconductor device 10 or other substrate.

Continuing with reference to FIGS. 11 and 12, wafer 72 or the one ormore semiconductor devices 10 or other substrates on platform 90 maythen be submerged partially below the surface level 88 of liquidmaterial 86 to a depth greater than the thickness of a first layer ofmaterial 86 to be at least partially consolidated (e.g., cured to atleast a semisolid state) to form the lowest layer 130 of each dielectricjacket 52 at the appropriate location or locations on each semiconductordevice 10 or other substrate, then raised to a depth equal to the layerthickness, surface 88 of material 86 being allowed to become calm.Photopolymers that are useful as material 86 exhibit a desirabledielectric constant, low shrinkage upon cure, are of sufficient (i.e.,semiconductor grade) purity, exhibit good adherence to othersemiconductor device materials, and have a similar coefficient ofthermal expansion (CTE) to the material of conductive centers 46, 56(FIGS. 1-6) (e.g., solder or other metal or metal alloy, conductiveresin, or conductive elastomer). Preferably, the CTE of material 86 issufficiently similar to that of the material of conductive centers 46,56 to prevent undue stressing thereof during thermal cycling ofsemiconductor device 10 or substrate 20 in testing, subsequentprocessing, and subsequent normal operation. Exemplary photopolymersexhibiting these properties are believed to include, but are not limitedto, the above-referenced resins from Ciba Specialty Chemicals Inc. Onearea of particular concern in determining resin suitability is thesubstantial absence of mobile ions and, specifically, fluorides.

Laser 92 is then activated and scanned to direct beam 98, under controlof computer 82, toward specific locations of surface 88 relative to eachsemiconductor device 10 or other substrate to effect the aforementionedpartial cure of material 86 to form a first layer 52A of each jacket 52.Platform 90 is then lowered into reservoir 84 and raised a distanceequal to the desired thickness of another layer 52B of each jacket 52,and laser 92 is activated to add another layer 52B to each jacket 52under construction. This sequence continues, layer by layer, until eachof the layers of jackets 52 have been completed.

In FIG. 12, the first layer of a dielectric jacket 52 is identified bynumeral 52A, and the second layer is identified by numeral 52B.Likewise, the first layer of base support 122 is identified by numeral122A and the second layer thereof is identified by numeral 122B. Asillustrated, both base support 122 and jacket 52 have only two layers.Jackets 52 with any number of layers are, however, within the scope ofthe present invention.

Each layer 52A, 52B of a dielectric jacket 52 is preferably built byfirst defining any internal and external object boundaries of that layerwith laser beam 98, then hatching solid areas of jacket 52 locatedwithin the object boundaries with laser beam 98. An internal boundary ofa layer may comprise aperture 54, a through-hole, a void, or a recess injacket 52, for example. If a particular layer includes a boundary of avoid in the object above or below that layer, then laser beam 98 isscanned in a series of closely-spaced, parallel vectors so as to developa continuous surface, or skin, with improved strength and resolution.The time it takes to form each layer depends upon the geometry thereof,the surface tension and viscosity of material 86, and the thickness ofthat layer.

Alternatively, dielectric jackets 52 may each be formed as a partiallycured outer skin extending above surface 14 of semiconductor device 10or above surface 24 of substrate 20 and forming a dam within whichunconsolidated material 86 can be contained. This may be particularlyuseful where the jackets 52 protrude a relatively high distance 60 fromsurface 14. In this instance, support platform 90 may be submerged sothat material 86 enters the area within the dam, raised above surfacelevel 88, and then laser beam 98 activated and scanned to at leastpartially cure material 86 residing within the dam or, alternatively, tomerely cure a “skin” comprising the surface of dielectric jackets 52, afinal cure of the material of the jackets 52 being effected subsequentlyby broad-source UV radiation in a chamber or by thermal cure in an oven.In this manner, jackets 52 of extremely precise dimensions may be formedof material 86 by apparatus 80 in minimal time.

When dielectric jackets 52″, depicted in FIG. 8, are being fabricated ona substrate, such as semiconductor device 10, having a conductive center56″ already secured to the contact pads 12 thereof, some of material 86may be located in shadowed areas 53 (see FIG. 8). As laser beam 98 isdirected substantially vertically downwardly toward surface 88 ofmaterial 86, material 86 located in shadowed regions 53 will not becontacted or altered by laser beam 98. Nonetheless, the unconsolidatedmaterial 86 in shadowed areas 53 will become trapped therein as material86 adjacent to and laterally outward from shadowed areas 53 is at leastpartially consolidated and as jacket 52 is built up around conductivecenter 56″. Such trapped, unconsolidated material 86 will eventuallycure due to the cross-linking initiated in the outwardly adjacentphotopolymer, and the cure can be subsequently accelerated as known inthe art, such as by a thermal cure.

Once dielectric jackets 52, or at least the outer skins thereof, havebeen fabricated, platform 90 is elevated above surface level 88 ofmaterial 86 and platform 90 is removed from apparatus 80, along with anysubstrate (e.g., semiconductor device 10, wafer 72 (see FIG. 10), orother substrate) disposed thereon and any stereolithographicallyfabricated structures, such as jackets 52. Excess, unconsolidatedmaterial 86 (e.g., excess uncured liquid) may be manually removed fromplatform 90, from any substrate disposed thereon, and from jackets 52.Each semiconductor device 10, wafer 72, or other substrate is removedfrom platform 90, such as by cutting the substrate free of base supports122. Alternatively, base supports 122 may be configured to readilyrelease semiconductor devices 10, wafers 72, or other substrates. Asanother alternative, a solvent may be employed to release base supports122 from platform 90. Such release and solvent materials are known inthe art. See, for example, U.S. Pat. No. 5,447,822 referenced above andpreviously incorporated herein by reference.

Jackets 52 and semiconductor device 10 or substrate 20 may also becleaned by use of known solvents that will not substantially degrade,deform, or damage jackets 52 or a substrate to which jackets 52 aresecured.

As noted previously, jackets 52 may then require postcuring. Jackets 52may have regions of unconsolidated material contained within a boundaryor skin thereof or in a shadowed area 53 (see FIGS. 8 and 9), ormaterial 86 may be only partially consolidated (e.g., polymerized orcured) and exhibit only a portion (typically 40% to 60%) of its fullyconsolidated strength. Postcuring to completely harden jackets 52 may beeffected in another apparatus projecting UV radiation in a continuousmanner over jackets 52 or by thermal completion of the initial,UV-initiated partial cure.

It should be noted that the height, shape, or placement of each jacket52 on each specific semiconductor device 10 or other substrate may vary,again responsive to output of camera 140 or one or more additionalcameras 144, 146, or 148, shown in broken lines, detecting theprotrusion of unusually high (or low) preformed, preplaced conductivecenters 56 which could affect the desired distance that jackets 52 willprotrude from surface 14. Likewise, the lateral extent (i.e., diameteror width) of each preplaced conductive center may be recognized and thegirth of the outer boundary of each jacket 52 adjusted accordingly. Inany case, laser 92 is again activated to at least partially curematerial 86 residing on each semiconductor device 10 or other substrateto form the layer or layers of each jacket 52.

Although FIGS. 11 and 12 illustrate the stereolithographic fabricationof jackets 52 on a substrate, such as a semiconductor device 10, a wafer72 (FIG. 10), or another substrate, including a plurality ofsemiconductor devices 10 or other substrates, jackets 52 can befabricated separately from a substrate, then secured to a substrate byknown processes, such as by the use of a suitable adhesive material.

The use of a stereolithographic process as exemplified above tofabricate dielectric jackets 52 is particularly advantageous since alarge number of jackets 52 may be fabricated in a short time, the jacketheight and position are computer controlled to be extremely precise,wastage of unconsolidated material 86 is minimal, solder coverage ofpassivation materials is avoided, and the stereolithography methodrequires minimal handling of semiconductor devices 10, wafers 72, orother substrates.

Stereolithography is also an advantageous method of fabricatingdielectric jackets 52 according to the present invention sincestereolithography can be conducted at substantially ambient temperature,the small spot size and rapid traverse of laser beam 98 resulting innegligible thermal stress upon semiconductor devices 10, wafers 72, orother substrates, as well as on the features thereof.

The stereolithography fabrication process may also advantageously beconducted at the wafer level or on multiple substrates, savingfabrication time and expense. As the stereolithography method of thepresent invention recognizes specific semiconductor devices 10 or othersubstrates 20, variations between individual substrates areaccommodated. Accordingly, when the stereolithography method of thepresent invention is employed, jackets 52 can be simultaneouslyfabricated on different types of semiconductor devices 10 or othersubstrates, as well as on both semiconductor devices 10 and othersubstrates.

Of course, other known methods can also be used to fabricate the jacketsof the conductive structures of the present invention. Exemplary methodsinclude, but are not limited to, the use of photoresist materials toform the reinforcement structures and fabrication of the reinforcementstructure from dielectric materials using known semiconductor devicepatterning (e.g., mask and etch) processes.

Fabricating Conductive Centers

Referring again to FIGS. 1-9, as disclosed previously herein, conductivecenters 46, 56 of members 40, 50 can be preformed or formed afterdielectric jackets 42, 52, respectively, have been secured to one ofsemiconductor device 10 and substrate 20. Preformed conductive centers46, 56 can be made by known processes, such as by molding quantities ofconductive material into a desired shape, then secured to a contact pad12, 22 of a semiconductor device 10 or substrate 20, respectively, byknown processes, such as by thermal bonding.

When conductive centers 46, 56 are formed after dielectric jackets 42,52 have been secured to contact pads 12 of semiconductor device 10 or tocontact pads 22 of substrate 20, conductive material is disposed in eachaperture 44, 54 in jackets 42, 52. Preferably, unconsolidated, molten,or uncured liquid conductive material is placed into apertures 44, 54.

When a solder, metal, or metal alloy is used to form conductive centers46, 56, molten material can be disposed into dielectric jackets 42, 52.As the melting temperatures of solders, metals, and metal alloys aretypically very high, it is preferred that the material from whichjackets 42, 52 are fabricated can withstand such temperatures withoutbeing damaged and without undergoing significant conformational ordimensional changes. For example, and not to limit the scope of thepresent invention, solder can be disposed in apertures 44, 54 bysubmerging jackets 42, 52 in a solder bath, after which the solder maybe allowed to harden and the conductive members secured to contact pads.Alternatively, when solder is used to form conductive centers 46, 56,solder paste or a preformed solder brick can be disposed in apertures44, 54, then subsequently reflowed to form conductive centers 46, 56.

Conductive thermoplastic materials can similarly be disposed inapertures 44, 54 in a melted state, then cooled to form conductivecenters 46, 56. As an alternative, particles of thermoplastic conductivematerial can be placed in apertures 44, 54 and heated and cooled to formconductive centers 46, 56. Such heating and cooling may be effectedeither before or after male member 40 and female member 50 areinterconnected.

Thermally curable conductive resins can also be disposed in apertures44, 54 in an uncured or partially uncured state, then heated to cure theconductive resin and to form conductive centers 46, 56. As indicatedpreviously herein, when thermally curable conductive resins are used,the conductive center 46, 56 of at least one of a pair of male andfemale members 40, 50 is left uncured or at least partially uncureduntil after male member 40 and female member 50 have been interconnectedso as to allow for the full curing of the conductive resin and theformation of an integral conductive center extending through conductivestructure 30.

Assembling a Semiconductor Device with a Substrate

Referring again to FIGS. 1 and 6, semiconductor device 10 is connectedto substrate 20 by aligning male members 40 protruding fromsemiconductor device 10 with corresponding female members 50 onsubstrate 20. The ends of male members 40 are then inserted into upperportion 58 of apertures 54 of their corresponding female members 50 suchthat the conductive centers 46 and 56 of male member 40 and femalemember 50, respectively, can communicate with one another. As notedpreviously herein, male member 40 may alternatively be secured tosubstrate 20 and female member 50 may alternatively be secured tosemiconductor device 10.

A single, integral conductive center can then be formed by bondingconductive centers 46 and 56. When conductive centers 46 and 56 areformed from a thermally curable conductive resin, at least one ofconductive centers 46, 56 is left at least partially uncured until malemember 40 and female member 50 are interconnected. The conductivematerial of conductive center 46, 56 can then be heated to a sufficientcuring temperature so as to bond conductive center 46 to conductivecenter 56. When conductive centers 46 and 56 comprise a thermoplasticconductive elastomer, a solder, a metal, or a metal alloy, conductivecenters 46 and 56 are heated to a sufficient temperature to wet orreflow the conductive material thereof and, thereby, to bond eachconductive center 46, 56 to its corresponding contact pad 12, 22 and tobond conductive center 46 to conductive center 56.

While the present invention has been disclosed in terms of certainpreferred embodiments, those of ordinary skill in the art will recognizeand appreciate that the invention is not so limited. Additions,deletions and modifications to the disclosed embodiments may be effectedwithout departing from the scope of the invention as claimed herein.Similarly, features from one embodiment may be combined with those ofanother while remaining within the scope of the invention.

1. A method for fabricating an electrical interconnection element foruse with a semiconductor device structure, comprising: providing atleast one substrate having at least one contact pad exposed at a surfacethereof; and disposing at least a first member of an electricalinterconnection element over the at least one contact pad, the firstmember having a conductive center and an insulative jacket configured tolaterally contain material of the conductive center over the at leastone contact pad, the first member being configured to connect with acomplementary second member of the electrical interconnection element.2. The method of claim 1, wherein disposing at least the first membercomprises securing the jacket to the at least one substrate with atleast a portion of the at least one contact pad being exposedtherethrough.
 3. The method of claim 2, further comprising: disposingthe conductive center in communication with the at least one contact padafter securing the jacket.
 4. The method of claim 3, wherein disposingthe conductive center comprises disposing at least partiallyunconsolidated conductive material in communication with the at leastone contact pad.
 5. The method of claim 4, wherein disposing at leastpartially unconsolidated conductive material comprises disposing atleast partially uncured conductive resin in communication with the atleast one contact pad.
 6. The method of claim 4, wherein disposing atleast partially unconsolidated conductive material comprises disposingat least one of a solder paste, a molten solder, a metal, or a metalalloy, in communication with the at least one contact pad.
 7. The methodof claim 4, wherein disposing at least partially unconsolidatedconductive material comprises disposing an at least partially meltedconductive elastomer in communication with the at least one contact pad.8. The method of claim 3, wherein disposing the conductive centercomprises disposing a preformed conductive center in communication withthe at least one contact pad.
 9. The method of claim 1, whereindisposing at least the first member comprises positioning the jacketaround a conductive center secured to the at least one contact pad. 10.The method of claim 1, wherein disposing at least the first membercomprises fabricating the jacket on the surface.
 11. The method of claim10, wherein fabricating comprises fabricating the jacket from aphotopolymer.
 12. The method of claim 3, wherein fabricating comprisesfabricating the jacket as at least two adjacent, mutually adheredregions.
 13. The method of claim 1, wherein providing comprisesproviding at least one semiconductor device.
 14. The method of claim 13,wherein providing comprises providing at least one semiconductor waferwith a plurality of semiconductor dice.
 15. The method of claim 13,wherein providing comprises providing at least one of a ball grid arraypackage and a chip-scale package.
 16. The method of claim 1, whereinproviding comprises providing at least one carrier substrate.
 17. Themethod of claim 1, wherein disposing comprises securing the jacket tothe surface.
 18. The method of claim 17, further comprising: prior todisposing, fabricating the jacket to have at least two adjacent,mutually adhered regions.
 19. The method of claim 18, whereinfabricating comprises fabricating at least one of the at least tworegions from a photopolymer material.
 20. A method for fabricating asemiconductor device component, comprising: providing at least onesubstrate with at least one contact pad exposed at a surface thereof;and sequentially forming at least one region of at least one jacket of afirst member of a conductive structure on the surface around the atleast one contact pad, the at least one jacket having an aperture formedthrough the length thereof and configured to laterally containconductive material over the at least one contact pad, the at least onejacket configured to interconnect with a jacket of a second member ofthe conductive structure.
 21. The method of claim 20, whereinsequentially forming comprises forming the at least one region from aphotopolymer.
 22. The method of claim 20, wherein providing comprisesproviding at least one semiconductor device.
 23. The method of claim 22,wherein providing comprises providing at least one wafer including aplurality of semiconductor dice.
 24. The method of claim 22, whereinproviding comprises providing at least one of a ball grid array packageand a chip-scale package.
 25. The method of claim 20, wherein providingcomprises providing at least one carrier substrate.
 26. The method ofclaim 20, wherein sequentially forming comprises forming the aperture tohave a larger periphery at an upper portion thereof than at a baseportion thereof.
 27. The method of claim 26, wherein forming comprisesforming an inner ledge between the upper portion and the base portion.28. The method of claim 26, wherein forming comprises forming at least aportion of a wall of the aperture to taper inwardly from the upperportion to the base portion.
 29. The method of claim 20, whereinsequentially forming comprises forming the at least one jacket to havean outer surface with a smaller periphery at an end thereof than at abase portion thereof.
 30. The method of claim 29, wherein formingcomprises forming an outer ledge on the outer surface between the endand the base portion.
 31. The method of claim 29, wherein formingcomprises forming at least a portion of the outer surface to taperoutwardly from the end to the base portion.
 32. The method of claim 31,wherein forming comprises forming the at least one jacket to have afrustoconical configuration.
 33. The method of claim 20, furthercomprising: disposing conductive material in the aperture.
 34. Themethod of claim 33, wherein disposing comprises substantially fillingthe aperture with the conductive material.
 35. The method of claim 33,wherein disposing comprises partially filling the aperture with theconductive material.
 36. The method of claim 35, wherein sequentiallyforming comprises forming the aperture to receive at least an end of thesecond member.
 37. The method of claim 33, wherein disposing comprisesdisposing at least partially unconsolidated conductive material in theaperture.
 38. The method of claim 37, wherein disposing comprisesdisposing at least partially uncured conductive resin in the aperture.39. The method of claim 37, wherein disposing at least partiallyunconsolidated conductive material comprises disposing at least one of asolder paste, a molten solder, a metal, and a metal alloy in theaperture.
 40. The method of claim 37, wherein disposing at leastpartially unconsolidated conductive material comprises disposing an atleast partially melted conductive elastomer in the aperture.
 41. Themethod of claim 20, further comprising: securing a preformed conductivecenter to the at least one contact pad.
 42. The method of claim 41,wherein securing the preformed conductive center is effected before thesequentially forming.
 43. The method of claim 41, wherein securing thepreformed conductive center is effected after the sequentially forming.44. A method for fabricating a semiconductor device component,comprising: placing at least one substrate with contact pads in ahorizontal plane; recognizing a location and orientation of the at leastone substrate; and fabricating at least one jacket of a first member ofa conductive structure by selectively consolidating material of the atleast one jacket in a manner controlled by a program, the first membercomprising at least one region of at least semisolid material on asurface of the at least one substrate, the at least one jacket around atleast one contact pad of the contact pads, the at least one jacketprotruding from the surface so as to laterally contain conductivematerial of a conductive center of the first member over at least aportion of the at least one contact pad, the first member beingconfigured to connect with a complementarily configured second member ofthe conductive structure.
 45. The method of claim 44, furthercomprising: storing data including at least one physical parameter ofthe at least one substrate and of the at least one jacket in computermemory, and using the stored data in conjunction with a machine visionsystem to recognize the location and orientation of the at least onesubstrate.
 46. The method of claim 45, further including, in computermemory, at least one physical parameter of the at least one contact padaround which the at least one jacket is to be fabricated.
 47. The methodof claim 45, further including, in computer memory, at least oneparameter of another substrate component with which the at least onesubstrate is to be assembled.
 48. The method of claim 45, furthercomprising: using the stored data, in conjunction with the machinevision system, to effect fabricating the at least one jacket.
 49. Themethod of claim 44, further comprising: recognizing a location of the atleast one contact pad.
 50. The method of claim 44, further includingsecuring the at least one substrate to a carrier prior to placing the atleast one substrate in the horizontal plane.